Instruction Cache Designs for a Class of Statically Scheduled Instruction Level Parallel Architectures

Statically-scheduled architectures such as very long instruction word (VLIW) architectures use very wide instruction words in conjunction with high bandwidth to the instruction cache to achieve multiple instruction issue. The encoding used for the instructions can have an e ect on the requirements placed on the instruction fetch and instruction cache hardware. One type of encoding is a compressed encoding , named so because it does not explicitly store NOPs within the wide instruction word. A compressed encoding enables high memory utilization but at the expense of variable-sized instructions and the complexities associated with fetching variable-sized instructions. This paper examines instruction fetch and instruction cache mechanisms for VLIW architectures that use compressed encodings. Relevant issues are investigated using the TINKER experimental testbed. A taxonomy for instruction caches for VLIW architectures that use a compressed encoding is introduced. Four cache organizations from di erent categories within the taxonomy are presented: the uncompressed cache, the banked cache, the rigid silo cache, and exible silo cache. The designs are evaluated using trace-driven simulations. The results indicate that the banked cache is the best performer in terms of storage area requirements/program performance, and the silo cache designs could be appropriate in designs where storage limitations are not an issue or the characteristics of the applications to be executed are well-known.